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MarciBE
Приєднався 27 тра 2012
BJT transistor as a switch - why you should bias it in the saturation region
BJT transistors should be biased in the saturation region when using them as switches. There are two reasons for this:
- Power consumption
- Safety
I also explain where the saturation region gets its name from.
- Power consumption
- Safety
I also explain where the saturation region gets its name from.
Переглядів: 730
Відео
CMOS Schmitt trigger - a step-by-step qualitative analysis
Переглядів 11 тис.5 років тому
Detailed qualitative analysis of the workings of the CMOS Schmitt trigger. I couldn't find a UA-cam video explaining the CMOS Schmitt trigger in detail, so I made one. This video is mainly about showing you why this is a Schmitt trigger and where the positive feedback mechanism comes into play. There are enough videos explaining how the CMOS inverter works and how an (OPAMP) Schmitt trigger fun...
Thanks for the video! Great lesson!
Thank you for this great insight! I have a question over the same current flows thru Mn1 and Mn2 (@ 15:58 min) where you show a graph that higher VDS is required for Mn2 in comparison to that of Mn2, right ? but actually the value of I2 = I1 + I4, right ? so I1 is not equal to I2 ! can you explain it please ? thanks!
I'm glad I could help! As I wrote in my description: 15:10 - I should have looked at the current in the triode region, but the conclusion remains the same. VDS over these transistors is low and therefore you have to look at the part that is close to (0,0) in the graph, which resembles V = RI of a transistor. You are right that the currents are not the same. What matters is that R2 > R1, which is why Vout - V2 increases.
So if we want to set the thresholds and hysteresis, if my understanding is correct, vout rising th is VIN= is [3.3-Vth(M1 or M2) ]/2 and Vout falling th is VIN = [ 3.3+Vth(M3 or M4)] /2
Yes, this seems to be correct. However, I would suggest you check this beforehand in simulation just to make sure.
Why is the other threshold 2.2V? shouldn't it be 2V -> (vdd+vth)/2 = 2V?
Yes, if the first threshold is 1.3 V, then by symmetry the other one should be 3.3 - 1.3 = 2 V. But again, check in simulation first to make sure you get what you expect.
Finally understood. Thanks.
Wow! awesome analysis. Keep it up and keep going. Cheers!
Dikke s/o naar u van een ingenieursstudent die overmorge examen elektronica heeft 🙏🏻🙏🏻
Succes bij Maarten!
for Vin=3.3V and power sypply also 3.3 won't Vsg= 0 and hehnce pmos M1 be off?
Yes, you are right. There will only be current once Vin gets below 2.6 V. But until that point, the voltage V1 will be 0.7 V. I mention in 5:15 that the diode and hence also the PMOS are on the "verge of conducting". Hope this makes it more clear! EDIT: The result I got in 8:33 is thus only true if Vin < 2.6 V. So that's a mistake on my part.
Thank you sir
Make a video on pseudostatic latch, c2mos lath
I want more videos like this! When will be your next one?